The present disclosure relates to an electronic device.
In an electronic device such as a solid-state imaging device having a structure in which a plurality of sensors such as CMOS image sensors are arranged in a two-dimensional matrix, a demand for advancement and miniaturization of signal processing is increasing. In order to realize the demand, for example, Japanese Unexamined Patent Application Publication No. 2011-159958 has proposed a method in which a large signal processing circuit is integrated within a semiconductor chip having a size which is equivalent to that in the related art by providing a plurality of semiconductor chips in a lamination structure. Specifically, the method has a lamination structure in which a semiconductor chip (hereinafter, may also be called “first semiconductor chip”) equipped with a sensor portion (sensor array) in which multiple sensors generating analog signals are arranged in a two-dimensional matrix is laminated on a chip (hereinafter, may also be called “second semiconductor chip”) equipped with a logic circuit for signal processing. Various circuits configuring the first semiconductor chip and various circuits configuring the second semiconductor chip are connected to each other by a through contact (Silicon) VIA (TC(S)V) formed in the first semiconductor chip, for example. Thus, miniaturization of the electronic device is realized by laminating the plurality of semiconductor chips in this manner.